![]() Half are in white DDR4 slots, and half are in black DDR4 slots, alternating on each side of the CPU. This is an example of a 2DPC configuration. Here we can see a total of 32 DIMMs installed. ![]() This Dell system is a fairly high-end system with four NVIDIA A100 SXM GPUs and two AMD EPYC 7763 CPUs (“Milan” generation). Dell EMC PowerEdge XE8545 AMD EPYC 7763 CPUs And Memory In the image below from our Dell PowerEdge XE8545 review, we can see this easily. The first DIMM generally provides the memory bandwidth from a memory channel being activated, but the second DIMM in each channel is there to add capacity. In modern CPUs, each DDR memory channel can host up to two DIMMs, with a catch. After doing dozens of calls, I wanted to just put this perspective out there. ![]() Many have come to me with a perspective informed by logic we would have used in the 2012-2019 server era, but that applies less today and will apply less in the future. Something I have received many calls about from the financial folks is the two DIMMs per channel (2DPC) operation of AMD EPYC 9004 “Genoa” CPUs. Theoretical DDR5 Memory Bandwidth Per Socket By Number Of DIMMs Populated Intel Sapphire Rapids V AMD EPYC Genoa DDR5 3600 Case
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